Not applicable.
Not applicable.
1. Field of the Invention
This invention relates generally to logic gates. More particularly, the invention relates to a high-fanin NOR gate that does not require a synchronization event before the output can be sampled.
2. Background Art
In digital circuits, it is often necessary to generate the logical NOR of a large number of input signals. Such circuits with a large number of inputs are often referred to as high fanin circuits. Example circuits include zero detect circuits in Arithmetic Logic Units (ALUs), Cache Tag Comparators, and Programmable Logic Arrays, where the number of inputs can be 16 or more.
For power and speed considerations, the conventional implementation of such a NOR logic gate is a dynamic MOS NOR circuit. The output node of the dynamic MOS NOR circuit is pre-charged to a known high state. If any input to the circuit is active (or true or logic xe2x80x9c1xe2x80x9d), the output switches to a low state.
A scenario of special interest is that in which all the circuit inputs are inactive, as in the case of a zero detector designed to detect all zeroes for a number of input signals. In this case, the conventional MOS NOR gate makes no state change on its output. Therefore, it is difficult to distinguish the pre-charged state from the evaluated, all zero input state by observing only the output. Often, it is necessary for an external agent to make the distinction based on an elapsed time period. For example, once the output pre-charge is complete, the external agent observes the output node after an elapsed time-period. If the output is still in the pre-charged state, then the logic gate has probably evaluated a complete set of inputs, and the all-zero case is in effect. The arbitrary point (in time) of evaluation is often referred to as a synchronization point or a synchronization event.
The issue is how much elapsed time is enough before the synchronization event? If the elapsed time interval is too short, then the circuit output might be erroneously sampled before all the inputs have been updated. If the interval is too long, then valuable time is wasted. As processor clock frequencies increase, it is extremely important not to waste time in delay paths.
The present invention is directed toward a method, system, and apparatus for detecting an all-zero scenario for an n-bit word. The all-zero scenario occurs when all bits of the n-bit word are determined to be logic xe2x80x9c0xe2x80x9d.
According to the invention, a high-inactive convention is defined for a selected bit of the n-bit word, and a high-active convention is defined for the remaining bits of the n-bit word. The high-inactive convention represents a logic xe2x80x9c0xe2x80x9d as a voltage high and represents a logic xe2x80x9c1xe2x80x9d as a voltage low. The high-active convention represents a logic xe2x80x9c0xe2x80x9d as a voltage low and represents a logic xe2x80x9c1xe2x80x9d as a voltage high. The invention generates a pre-charge voltage during a low clock cycle. During a high clock cycle, the invention evaluates the logic state of the selected bit using the high-inactive convention, and the logic state of the non-selected bits using the high-active convention. Specifically, the invention determines the voltage of the selected bit, and each of the non-selected bits. The invention discharges the pre-charge voltage if the selected bit is a voltage high, and each of the non-selected bits is a voltage low, whereby the discharge of the pre-charge voltage indicates the all-zero scenario. The invention maintains the pre-charge voltage if the selected bit is a voltage low or any one of the non-selected bits is a voltage high.
In one embodiment, the invention is implemented in an output synchronization-free NOR gate. The NOR gate includes an output FET, a pre-charging circuit, a first evaluation circuit, and (nxe2x88x921) second evaluation circuits.
The NOR gate operates as follows. During the low clock cycle, the pre-charging circuit charges the output FET gate, drain, and source to a pre-charge voltage. An inverter inverts the pre-charge voltage on the output FET drain, producing a voltage low on the NOR gate output during the low clock cycle.
During the high clock cycle, the first evaluation circuit evaluates the selected bit, and the second evaluation circuits evaluate their corresponding non-selected bits. The first evaluation circuit discharges the pre-charge voltage on the output FET source if the selected bit is a voltage high. The (nxe2x88x921) second evaluation circuits maintain the pre-charge voltage on the output FET gate if each of the non-selected bits is a voltage low. The output FET conducts (i.e., is ON) if the pre-charge voltage is maintained on the output FET gate and if the output FET source is discharged to a low voltage. The drain of the output FET discharges to a low voltage when the output FET conducts, which indicates the all-zero scenario. The inverter coupled to the output FET drain inverts the voltage on the output FET drain, producing a transition from a voltage low to a voltage high on the NOR gate output for the all zero scenario.
If the selected bit is voltage low, then the first evaluation circuit maintains the pre-charge voltage on the output FET source, thereby preventing the output FET from conducting. If one or more of the non-selected bits is a voltage high, then the respective second evaluation circuit (with the high input) discharges the gate voltage on the output FET, thereby preventing the output FET from conducting.
In one embodiment, the first evaluation circuit includes a means for adjusting the discharge rate of the output FET source voltage, as a function of the output FET gate voltage. More specifically, the source discharge rate varies inversely with gate voltage. This prevents the unintentional spurious conduction of the output FET when both the source and gate of the output FET are being discharged, simultaneously.
An advantage of the present invention is that the NOR gate output can be sampled without requiring a synchronization event. This results because the NOR gate output is a voltage low during the low clock cycle. The NOR gate output transitions from a voltage low to a voltage high during the high clock cycle only when the all-zero scenario is detected. As such, the NOR gate output for the all-zero scenario is distinct from that of the low clock cycle, and therefore no synchronization event is necessary before sampling the NOR gate output.